1. Technical Field of the Invention
The present invention relates to the field of voltage regulators and in particular to regulators with a low drop-out.
2. Description of the Related Art
A low drop-out regulator made in an integrated circuit may be used to provide a predetermined voltage with low noise to a set of electronic circuits from a supply voltage provided by a rechargeable battery. Such a supply voltage decreases in time and is likely to include noise due for example to the action of neighboring electromagnetic radiations on the battery-to-regulator connections. The regulator is said to have a low drop-out since it enables providing a voltage close to the supply voltage.
FIG. 1 schematically shows a conventional low drop-out regulator. The regulator includes an output terminal 2 intended for being connected to a load R. Load R, essentially resistive, represents the input impedance of the set of the circuits supplied by the regulator. For simplicity, it is considered hereafter that load R is a resistor. The regulator includes an operational amplifier 4 having a non-inverting input E+ connected to a positive reference voltage Vref and having an inverting input E− connected to output terminal 2 by a feedback loop. Voltage Vref is generated in a known manner by a constant voltage source (not shown) with a high output impedance. Operational amplifier 4 is supplied between a positive supply voltage Vbat provided by the battery and a ground voltage GND. An inverting amplifier 6 supplied between voltages Vbat and GND has an input terminal connected to the output of operational amplifier 4. A capacitor C1 and a resistor R1 are connected in series between the input terminal and the output terminal of amplifier 6. A P-channel MOS power transistor T1 has its drain connected to output terminal 2 and its source connected to voltage Vbat. The gate of transistor T1 is connected to the output terminal of inverting amplifier 6. Transistor T1 is of MOS type, especially to minimize, with respect to the use of a bipolar transistor, the difference between output voltage Vout of terminal 2 and supply voltage Vbat. A charge capacitor C is arranged between output terminal 2 and voltage GND.
The regulator maintains the voltage of output terminal 2 to a value equal to reference voltage Vref. Any variation in voltage Vbat translates as a variation in voltage Vout, which is transmitted by the feedback loop on input E−. When the regulator operates properly, the variation in the voltage of terminal E− causes the return of voltage Vout to voltage Vref. For this purpose, the regulator circuit, which forms a looped system between input E− and terminal 2, must form a stable system. The stability of a system is evaluated by considering the gain and the phase shift introduced by the system between its input and its output when the system is in open loop. For this system to be stable when looped, the gain must not exceed 1 when the phase shift is smaller than −180° (phase opposition between the system input and output).
FIG. 2 illustrates, according to frequency f, the variation of gain G and of phase shift φ of the open-loop regulator between input E− and terminal 2. For low frequencies f, gain G is equal to static gain G0 of the open-loop regulator. The elements forming the regulator each have a gain which varies according to the frequency. The cut-off frequency of an element having a gain that decreases when the frequency increases corresponds to a “pole” of the transfer function of the open-loop regulator. The cut-off frequency of an element having a gain that increases when the frequency increases corresponds to a “zero” of the transfer function of the open-loop generator. Each pole and each zero of the transfer function of the open-loop regulator respectively introduces a drop and an increase of 20 dB per decade in gain G. Further, each pole and each zero of the transfer function of the open-loop regulator respectively introduces a 90° drop and increase in phase shift φ. For simplicity, it is considered hereafter that the transfer function of the open-loop regulator only includes one main pole P0, two secondary poles P1 and P2, and one zero Z1. The value of main pole P0 especially depends on the inverse of the product of the values of load resistance R and of capacitance C. The value of secondary pole P1 especially depends on the gate impedance of amplifier 6. The value of secondary pole P2 especially depends on the gate capacitance of transistor T1. The values of poles P1 and P2 also depend on the gain of amplifier 6 and on the value of capacitance C1. Inverter amplifier 6 assembled in parallel with a capacitive impedance forms a stage known as a “Miller stage”. Such a stage results in decreasing the value of secondary pole P1 and increasing the value of secondary pole P2. The distance between poles P1 and P2 increases with the gain of amplifier 6 and the capacitance of capacitor C1. The value of zero Z1 especially depends on the existing ratio between the values of resistance R1 and of capacitance C1. The choice of the gain of amplifier 6, of capacitor C1, and of resistor R1 enables adjusting the positions of poles P1 and P2 and of zero Z1 so that, when phase shift φ becomes equal to −180°, gain G is smaller than the unity gain (0 dB). In FIG. 2, pole P0 is at a low frequency, pole P1 is at a greater frequency than pole P0, and pole P2 is at a frequency greater than pole P1. Zero Z1, close to pole P1, is located between poles P1 and P2. For a frequency smaller than the frequency of pole P0, the gain is equal to static gain G0 of the open-loop regulator. Between poles P0 and P1, the gain drops by 20 decibels per decade. Between pole P1 and zero Z1, the gain drops by 40 decibels per decade. Between zero Z1 and pole P2. the gain drops by 20 decibels per decade, and beyond pole P2, the gain drops by 40 decibels per decade. The phase shift drops from 0 to −90° at pole P0. The phase shift decreases under −90°, then returns to −90° at pole P1 and zero Z1. The phase shift drops from −90° to −180° at pole P2.
A disadvantage of such a regulator is that the value of load resistance R, which represents the input impedances of integrated circuits, decreases when the output current flowing through load R increases. This decrease in resistance R translates as a shift of main pole P0 towards high frequencies and in a shift to the right of the gain curve, as illustrated in dotted lines by curve G′. This may result in a gain G′ with a value greater than 1 (0 dB) when phase-shift φ′ reaches value −180°. A stable conventional regulator for a low output current may also be unstable for a strong output current. It is difficult to form a stable regulator over the entire output current range.